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DM74S161 * DM74S163 Synchronous 4-Bit Binary Counters
August 1986 Revised April 2000
DM74S161 * DM74S163 Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. They are 4-bit binary counters. The carry output is decoded by means of a NOR gate, thus preventing spikes during the normal counting mode of operation. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count enable inputs and internal gating. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positivegoing) edge of the clock input waveform. These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a LOW level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable input. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be HIGH to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a HIGH-level output pulse with a duration approximately equal to the HIGH-level portion of the QA output. This HIGH-level overflow ripple carry pulse can be used to enable successive cascaded stages.
Features
s Synchronously programmable s Internal look-ahead for fast counting s Carry output for n-bit cascading s Synchronous counting s Load control line s Diode-clamped inputs
Ordering Code:
Order Number DM74S161N DM74S163N Package Number N16E N16E Package Description 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS006471
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DM74S161 * DM74S163
Logic Diagram
DM74S161 * DM74S163
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DM74S161 * DM74S163
Timing Diagram
Sequence: 1. Clear outputs to zero 2. Preset to binary twelve 3. Count to thirteen, fourteen, fifteen, zero, one and two 4. Inhibit
3
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DM74S161 * DM74S163
Parameter Measurement Information
Switching Time Waveforms
Note A:The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50%, ZOUT 50. For DM74S161/163, t r 2.5 ns, tf 2.5 ns. Vary PRR to measure fMAX . Note B: Outputs QDand carry are tested at tn + 16 for DM74S161, SM74S163 where tn is the bit time when all outputs are LOW Note C: VREF = 1.5V.
Switching Time Waveforms
Note A: The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50%, ZOUT 50. t r 2.5 ns, tf 2.5 ns. Vary PRR to measure fMAX. Note B: Enable P and enable T setup times are measured at tn + 0. Note C:VREF = 1.5V.
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DM74S161 * DM74S163
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 5.5V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Pulse Width (Note 2) Pulse Width (Note 3) tSU Setup Time (Note 2) Clock Clear (Note 5) Clock Clear (Note 5) Data Enable P or T Load Clear (Note 4) Setup Time (Note 3) Data Enable P or T Load Clear (Note 4) tH Hold Time (Note 2) Hold Time (Note 3) tREL TA Data Others Data Others Load or Clear Release Time (Note 2) Load or Clear Release Time (Note 3) Free Air Operating Temperature
Note 2: CL = 15 pF, RL = 280, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, RL = 280, TA = 25C and VCC = 5V. Note 4: Applies only to the DM74S163 which has synchronous clear inputs. Note 5: Applies only to the DM74S161 which has asynchronous clear inputs.
Parameter
Min 4.75 2
Nom 5
Max 5.25 0.8 -1 20
Units V V V mA mA MHz ns
0 0 10 10 12 12 4 12 14 14 5 14 16 16 3 0 5 2 12 14 0
40 35
ns
ns
ns 70 C
5
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DM74S161 * DM74S163
Electrical Characteristics
over recommended operating free air temperature (unless otherwise noted) Symbol VI VOH VOL II IIH IIL IOS ICC Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage LOW Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIH = Min, VIL = Max VCC = Max VI = 2.7V VCC = Max VI = 0.5V VCC = Max (Note 7) VCC = Max CLK, Data Others Enable T Others -40 95 -10 2.7 3.4 0.5 1 50 -200 -4 -2 -100 160 mA mA Min Typ (Note 6) Max -1.2 Units V V V mA A mA
Input Current @ Max Input Voltage VCC = Max, VI = 5.5V
Note 6: All typicals are at VCC = 5V, TA = 25C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Switching Characteristics
at VCC = 5V and TA = 25C RL = 280 Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPHL Parameter Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time HIGH-to-LOW Level Output (Note 8) Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q Clock to Any Q Enable T to Ripple Carry Enable T to Ripple Carry Clear to Any Q From (Input) To (Output) CL = 15 pF Min 40 25 25 15 15 15 15 20 Max CL = 50 pF Min 35 25 28 15 18 18 18 24 Max MHz ns ns ns ns ns ns ns Units
Note 8: Propagation delay for clearing is measured from clear input for the DM74S161 and from the clock input transition for the DM74S163.
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DM74S161 * DM74S163 Synchronous 4-Bit Binary Counters
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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